Multi-valued ROM circuit #7

ABSTRACT

A semiconductor circuit which realizes a read-only memory cell having zero stand-by power consumption and capable of non-volatile storage of multiple-valued or analog data. This semiconductor device is comprises of at least a single-channel or p-channel MOS transistor in a source-follower circuit configuration. The input of this source-follower circuit is a floating gate which is capacitively coupled to multiple control gates. The voltages applied to the control gates and the coupling ratios of the control gates determine the potential of the floating gate. When a voltage supply is applied to the drain electrode of the source-follower circuit, the source-electrode potential will nearly equal the floating gate potential.

TECHNICAL FIELD

The present invention relates to a semiconductor device, and inparticular to a high-performance MOS circuit.

BACKGROUND ART

Source-follower circuits are frequently used to drive impedance loads,especially in applications employing analog or multiple-valued signals.Such a circuit is depicted in FIG. 1. This diagram indicates asource-follower circuit comprised of one NMOS transistor (abbreviated as"NMOS") (M10) and a load capacitance (C10); when V_(IN) (101) is greaterthan V_(T) (the threshold voltage of M10), current flows to increaseV_(OUT) (102) until

    V.sub.OUT =V.sub.IN -V.sub.T                               ( 1)

If the gate electrode of an NMOS in a source-follower configuration ismade floating, and several input gates are capacitively coupled to thefloating gate, as shown in FIG. 2, then the potential of the floatinggate (φF) (201) becomes a linearly weighted summation of the voltagesapplied to the inputs: ##EQU1## where n is the number of input gates, C₁to C_(n) are the coupling capacitances to the floating gate, andC_(total) is the sum of all coupling capacitances. Therefore, byadjusting the coupling capacitance ratios and the input voltages, thefloating gate potential can assume any desired voltage. In this circuit,V_(OUT) (202) will rise until it equals φF-V_(T).

One application of this circuit is the simple 2-bit digital-to-analog(D/A) converter depicted in FIG. 3. By setting the coupling ratio C₁ :C₂=1:2, and applying 0 V or 5 V to the input gates V₁ (301) and V₂ (302),four possible states are obtained on the floating gate (303), as shownin Table 1 shown in FIG. 13. In Table 1, the symbol "WL" designates ahigh level signal applied to the respective inputs, in this case, thehigh level signal is 5 V. In this manner, the digital signals at V₁ andV₂ are converted into analog signals at V_(OUT) (304).

DISCLOSURE OF THE INVENTION

The present invention discloses a semiconductor circuit comprising atleast a single n-channel or p-channel MOS transistor in asource-follower configuration. The input of this source-follower circuitis a floating gate which is capacitively coupled to multiple controlgates. The voltages applied to the control gates and the coupling ratiosof the control gates determine the potential of the floating gate. Whena voltage supply is applied to the drain electrode of thesource-follower circuit, the source-electrode potential will nearlyequal the floating gate potential, provided that V_(T) ≈0 in Equation 1.

The above semiconductor device realizes a single-transistor, read-onlymemory cell capable of non-volatile storage of multiple-valued or analogdata. The data is programmed into the cell by a single masking stepduring the fabrication process. This cell can be replicated into amatrix of several rows and columns, with all cells in one row sharing acommon word line and all cells in one column sharing a common bit line,thus achieving a high-density memory-cell array. Furthermore, this celldoes not consume any standby-by power.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a typical NMOS source-followercircuit.

FIG. 2 is a circuit diagram showing an NMOS source-follower circuit withmultiple input gates capacitively coupled to its floating gateelectrode.

FIG. 3 is a circuit diagram showing a 2-bit digital-to-analog converterusing a floating-gate NMOS source follower.

FIG. 4 is a circuit diagram showing the circuit of Embodiment 1, for thecase of storing the data value "2".

FIG. 5 is a circuit diagram showing the circuit of Embodiment 2, for thecase of storing the data value "2".

FIG. 6 is a circuit diagram showing the circuit of Embodiment 3, for thecase of storing the data value "2".

FIG. 7 is a circuit diagram showing a sample array of cells described byEmbodiment 3.

FIG. 8 shows measured operation data of the circuit of Embodiment 3.

FIG. 9 is a photomicrograph of 4-valued and 8-valued fabricated testcells.

FIG. 10 is a schematic diagram of the top-view and cross-section of theinvention.

FIG. 11 is a circuit diagram showing the circuit of Embodiment 4, forthe case of storing the data value "2".

FIG. 12 is a circuit diagram showing 8-valued cells which comparesprogramming with (a) binary-weighted capacitors and (b)variably-weighted capacitors of Embodiment 5.

FIG. 13 shows Table 1 which lists the four possible states on thefloating gate of the 2-bit digital to analog converter of FIG. 3.

BEST MODE FOR CARRYING OUT THE INVENTION

Herein below, the present invention will be explained in detail based onembodiments; however, the present invention is of course not limited tothese embodiments.

(Embodiment 1)

The single-transistor, 2-bit D/A converter of FIG. 3 can be convertedinto a memory cell by simply adding a select transistor (M40), as shownin FIG. 4. Table 1 lists the four possible state on the floating gate ofthe 2-bit digital-to-analog converter of FIG. 3. FIG. 4 depicts afour-valued cell which stores the data value "2". Different values canbe programmed into the cell by changing the connections of electrodes401 and 402 to either V_(DD) or 0 V. This is done by a single maskingstep in the device fabrication process. In this manner, varying statesare obtained on the floating gate (403), as given by Equation (2).

To read data from the cell, the bit line (404) is pre-charge to 0 V, andM40 is turned on by setting the word line (405) high. Therefore, currentfrom the source-follower (M41) raises the bit line voltage. If thethreshold voltage of M41 is zero, then the bit line voltage will riseuntil it equals the floating gate potential φF.

(Embodiment 2)

The cell of Embodiment 1 requires two transistors; however, this cellcan be reduced to a single transistor, as depicted in FIG. 5. If theinput gates are connected to either the word line (502) or 0 V, then M50does not turn on unless the word line is high. Therefore, current doesnot flow from the cell unless the word line is selected, eliminating theneed for a separate select transistor.

(Embodiment 3)

In Embodiment 2, a separate line (501) must carry the V_(DD) voltagesupply to all the cells in the memory array. The circuit shown in FIG. 6presents an alternative that further decreases the cell area. Byconnecting the drain electrode (601) of M60 to the word line, the V_(DD)line can be eliminated.

FIG. 7 shows an example of an array of four cells. This figure explainshow the cells can be arranged in a high density array by sharing commonword lines (701 and 702), 0 -V lines (703 and 704), and bit lines (705and 706).

Experimental data for the operation of the circuit in this embodiment isshown in FIG. 8. This data was taken from the fabricated 4-valued testdevices shown in FIG. 9. The micrograph in FIG. 9 shows 4-valued and8-valued cells.

FIG. 10 shows a schematic top-view and cross-section of a four-valuedcell. The first polysilicon layer forms the floating gate, and thesecond polysilicon layer forms the input coupling gates. However, theimplementation of this invention is not limited to this particulardevice structure.

In Embodiments 1, 2, and 3, the bit line is reset to 0 V before eachread operation, and an NMOS transistor is used in as a source-followercircuit. Alternatively, the bit line could be pre-charged to V_(DD), anda PMOS source-follower could be used to lower the bit line voltage.

Furthermore, in the above embodiments, leakage currents may flow inunselected cells due to subthreshold currents in the transistor. Thishappens when V_(T) ≈0 V and can lead to erroneous data readings. Tosolve this problem, a positive threshold voltage (for example, V_(T)=0.5 V) could be used instead. In this case, the output voltage willonly rise until φF -0.5 V. However, it is possible to employ sensingcircuitry which detects the reduced voltage level and restores theoriginal data, namely, φF.

(Embodiment 4)

The NMOS source-follower of Embodiment 1 could be replaced by a CMOSsource-follower circuit, consisting of an NMOS (M111) and a PMOS (M112),as depicted in FIG. 11. In this case, the bit line need not bepre-charged since the CMOS source-follower can drive the bit line toboth low and high levels, depending on the floating gate potential.

(Embodiment 5)

The number of possible values stored by this cell can be altered bychanging the number of binary-weighted input gates. For nbinary-weighted input gates, it is possible to store 2^(n) values in thecell. From Equation 2, the floating gate potential in the cell for thecase of n binary-weighted input gates is ##EQU2##

Alternatively, the number of possible values stored by this cell can bealtered by using variably-weighted coupling capacitances. In thismanner, an infinite number of states can be obtained on the floatinggate by using only two input gates and adjusting their coupling ratio.For this case, the floating gate potential is given by ##EQU3## Sinceany floating gate potential can be obtained by simply adjusting theratio k, this cell is capable of storing analog data.

FIG. 12 depicts 8-valued cells implemented by (a) binary-weightedcapacitors and (b) variably-weighted capacitors.

Furthermore, in the embodiments above, it is possible that charge willbe unintentionally injected onto the floating gate, thus shifting φFundesirably. To reset and remove the injected charge and reset thefloating gate potential, a switch may be attached to the floating gate.When the cell is in standby mode, the switch can be turned on to resetthe floating gate. When the cell is reading out data, the switch must beoff.

Furthermore, the embodiments described above can be implemented by usingfuses or anti-fuses to program the multivalued data in the cell afterthe completion of the fabrication process. This can be done instead ofmask programming.

INDUSTRIAL APPLICABILITY

By means of the present invention, it is possible to realize thenon-volatile storage of multiple-valued or analog data in a read-onlymemory cell. This cell can be replicated into a matrix of many rows andcolumns to achieve a high-density memory array.

This invention is especially suitable in systems dealing withmultiple-valued or analog information, such as image processors ormultiple-valued microprocessors.

What is claimed is:
 1. A multi-valued ROM circuit, comprising:an MOStransistor having a drain electrode, a source electrode and a floatinggate electrode, said drain electrode connected to a first signal linewhich provides a first voltage level, said source electrode connected toa bit line for providing a multi-valued output signal on said bit line,said floating gate electrode capacitively coupled to a plurality ofinput gates, each said input gate connected to one of a second signalline which carries a second voltage level and a third signal line whichis at 0 V to provide a weighted input based on one of said secondvoltage level and 0 V, said multi-valued output signal assuming apredetermined level in response to a combination of said weightedinputs.
 2. The multi-valued ROM circuit according to claim 1, whereinsaid MOS transistor is an NMOS transistor.
 3. The multi-valued ROMcircuit according to claim 1, wherein said MOS transistor is a PMOStransistor.
 4. A multi-valued ROM circuit, comprising:an MOS transistorhaving a source electrode, a drain electrode and a floating gateelectrode, said source electrode connected to a bit line for providing amulti-valued output signal on said bit line, said drain electrodeconnected to a word line which carries a first voltage level, saidfloating gate electrode capacitively coupled to a plurality of inputgate electrodes, each said input gate electrode connected to one of saidword line and a zero signal line which is at 0 V to provide a weightedinput based on one of said first voltage level and 0 V, saidmulti-valued output signal assuming a predetermined level in response toa combination of said weighted inputs.
 5. The multi-valued ROM circuitaccording to claim 4, wherein said MOS transistor is an NMOS transistor.6. The multi-valued ROM circuit according to claim 4, wherein said MOStransistor is a PMOS transistor.
 7. A multi-valued ROM circuit,comprising:a first MOS transistor having a source electrode, a drainelectrode and a floating gate electrode, said source electrode connectedto a bit line through a second MOS transistor for providing amulti-valued output signal on said bit line, said second MOS transistorhaving a gate electrode connected to a word line which carries a firstvoltage level, said drain electrode connected to a second signal linewhich carries a second voltage level, said floating gate electrodecapacitively coupled to a plurality of input gate electrodes, each saidinput gate electrode connected to one of said second signal line and athird signal line which is at 0 V to provide a weighted input based onone of said second voltage level and 0 V, said multi-valued outputsignal assuming a predetermined level in response to a combination ofsaid weighted inputs.
 8. The multi-valued ROM circuit according to claim7, wherein said MOS transistor is an NMOS transistor.
 9. Themulti-valued ROM circuit according to claim 7, wherein said MOStransistor is a PMOS transistor.